CPU ARCHITECTURE: fetch and decode, execute, fetch and decode, execute, ...

REGISTERS: A (000), B (001), C (010), D (011), MULH (100), MULL (101), SPH (110), SPL (111)
SPECIAL REGISTERS: Instruction Pointer (16 bits, MSB=0), Stack Pointer (16 bits, MSB=1), Address Pointer (16 bits, MSB=1), Multiplication Result (16 bits)
MEMORY: 15 bits ROM (lower 15 bits), 15 bits RAM (top 15 bits) (controlled by the 16bit address register)

STATUS register:
Carry (1 if last op had a carry/borrow), Sign (1 if last op returned negative), Zero (1 if last op returned 0), Parity (1 if odd)

instructions:
NOP (any unknown sequence of bits will be assumed as a NOP)
HLT (will be encoded as all 0s, first instruction)

PUSH (reg)
POP (reg)

LOAD (reg), (imm)

MOV (reg), (mem)
MOV (mem), (reg)
MOV (reg), (reg)

ADD (reg), (mem)
ADD (mem), (reg)
ADD (reg), (reg)

SUB (reg), (mem)
SUB (mem), (reg)
SUB (reg), (reg)

MUL (reg), (mem)
MUL (mem), (reg)
MUL (reg), (reg)

SMUL (reg), (mem) (signed)
SMUL (mem), (reg) (signed)
SMUL (reg), (reg) (signed)

SHL (reg) (unsigned)

SHR (reg) (unsigned)

CMP (reg), (mem)
CMP (mem), (reg)
CMP (reg), (reg)

JMP (reg) (all jumps are relative to current IP)
JMP (mem)

JE (reg)
JE (mem)

JNE (reg)
JNE (mem)

JG (reg) (signed)
JG (mem)

JGE (reg)
JGE (mem)

JL (reg)
JL (mem)

JLE (reg)
JLE (mem)

JA (reg) (unsigned)
JA (mem)

JAE (reg)
JAE (mem)

JB (reg)
JB (mem)

JBE (reg)
JBE (mem)